As shown in FIG. 1 is an example of using rechargeable battery protection circuit in conventional application such as secondary battery of PDA (Personal Data Assistance) and mobile phone, wherein the working principle of the protection IC is as follows: the first pin Cout controls the gate electrode Gate of power field effect transistor MOSFET on the discharge end to enable the charge of said battery pack; the second pin Ct is connected to an external capacitor to control the output delay time of a voltage inspection device; the third pin Vss is grounded; the fourth pin Dout is connected to the gate electrode Gate of power field effect transistor MOSFET on the discharge end so as to control the output current of a battery pack; the fifth pin Vdd is connected to a rechargeable battery end so as to monitor the voltage of said rechargeable battery and provide a power source of said protection circuit; the sixth pin V-monitors the discharge current of said battery pack, there is serially connected a short-circuit protection device to prevent said discharge current from becoming too large. As shown in FIGS. 2a and 2b, above mentioned protection circuit serially connects gate electrodes of two power field effect transistors obtained from standard packing process, wherein said gate electrodes are connected to a protection IC, and the source of one transistor is connected to the negative end of a rechargeable battery while the source of another transistor is connected to the negative end of a power supply. After completion of packing, all power field effect transistors contain a lead frame, which is soldered onto the protection circuit of circuit board.
However, due to the packing structure of the power field effect transistor, its volume is largely increased after welded onto the protection circuit, which not only affects battery volume but also has a much higher resistance in a packed power field effect transistor than that of a bare chip due to the resistance of lead frame itself. Therefore, the inventors have taken the omission of the welding wire and the packing steps of a power field effect transistor into consideration, and found that it is possible to use flip-chip mounting technique to lower not only the volume of a protection circuit but also the on-resistance of said power field effect transistor.
The official gazette of ROC Patent No. 366576 disclosed a “Method of configuring a flip-chip assembled lead frame for an integrated circuit device and a device formed therefrom”, which mainly comprises: an integrated circuit device having chip and lead frame; wherein the surface of said chip has a plurality of tin-contained metal bumps that electrically connected to the external, and said lead frame has a plurality of lead feet. The configuration steps will first metallurgy process areas of multiple lead feet carrying chip on said lead frame so that said lead-foot area has a tin-stained feature; align said areas of tin-stained lead feet to said plurality of tin-contained metal bumps on the chip, respectively; finally through heating and pressuring to fix said areas of tin-stained lead feet on said lead frame to said plurality of tin-contained metal bumps on the chip. However, above-mentioned flip-chip configuration still includes a lead frame, thereby increases the on-resistance of the chip.